This paper proposes the design and implementation of Booth multiplier using VHDL. This compares the power consumption and delay of radix 2 and modified radix 4 Booth Continue reading
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Tag: VHDL
Implementation of a Program Address Generator in a DSP Processor
The purpose of this study is to construct a “Program Address Generator”(PAG) to a 24-bit Harvard type, RISC DSP processor using the VHDL language. The PAG is a part of the Continue reading
Analysis of the MIPS 32-bit, Pipelined Processor using Synthesized VHDL
For large and complicated ASIC designs, it is difficult to read and understand the circuits based on schematic drawings alone; as a result, a hardware description language is Continue reading
Hardware Accelerator for Duo-binary CTC Decoding: Algorithm Selection, HW/SW Partitioning and FPGA Implementation
Wireless communication is always struggling with errors in the transmission. The digital data received from the radio channel is often erroneous due to thermal noise and fading. The error rate can be Continue reading
A VHDL Reaction Timer
This simple project will combine many advanced VHDL techniques including timers, seven segment display drivers, packages and functions, and state machines to create a Continue reading
Low Power 32×32 bit Multiplier Architecture based on Vedic Mathematics Using Virtex 7 Low Power Device
In this paper the most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Continue reading