Dismounted soldier power needs have changed significantly since fielding of the G-67B/G, a portable DC hand crank generator. A developmental hand crank system, with the potential for Continue reading
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Tag: Power Saving
Towards the Internet of Smart Trains: A Review on Industrial IoT-Connected Railways
ABSTRACT
Nowadays, the railway industry is in a position where it is able to exploit the opportunities created by the IIoT (Industrial Internet of Things) and enabling communication technologies under the paradigm of Internet of Trains. This review details the Continue reading
The Design of a Low Power Asynchronous Multiplier
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of Continue reading
BZ-FAD: A Low-Power Low-Area Multiplier based on Shift-and-Add Architecture
In this paper, a low-power structure called BZ-FAD (Bypass Zero, Feed A Directly) for shift-and-add multipliers is proposed. The architecture considerably lowers the Continue reading
Low Power and Low Complexity Shift-and-Add Based Computations
The main issue in this project is to minimize the energy consumption per operation for the arithmetic parts of DSP circuits, such as digital filters. More specific, the focus is on single- and multiple-constant multiplications, which are realized using Continue reading
A New Low Power 32×32-bit Multiplier
Multipliers are one of the most important building blocks in processors. This paper describes a low-power 32×32-bit parallel multiplier, designed and fabricated using Continue reading
Optimization of Power Consumption in VLSI Circuit
Space, power consumption and speed are major design issues in VLSI circuit. The design component has conflicting affect on overall performance of circuits. An optimization of power dissipation can be achieved by Continue reading
An Asynchronous Pipelined 32×32-bit Iterative Multiplier Using Hybrid Handshaking Protocol
An asynchronous pipelined 32×32-bit iterative multiplier is presented in this paper. The multiplier supports 32×32-bit integer multiplication of both signed and Continue reading
A High Speed and Low Power VLSI Multiplier using a Redundant Binary Booth Encoding
This paper presents a new high speed and low power multiplier that uses a new encoding scheme, taking advantage of Continue reading
Estimation of Peak Power Dissipation in VLSI Circuits Using the Limiting Distributions of Extreme Order Statistics
In this paper, we present a statistical method for estimating the peak power dissipation in VLSI circuits. The method is based on the theory of extreme order statistics applied to the probabilistic distributions of the cycle-by-cycle Continue reading
Low Power 32×32 bit Multiplier Architecture based on Vedic Mathematics Using Virtex 7 Low Power Device
In this paper the most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Continue reading