This project discusses the use of self-organizing maps in a diesel engine management system. Self-organizing maps are one type of artificial neural networks that Continue reading
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Tag: Algorithm
Efficient Decoding Algorithms for Low-Density Parity-Check Codes
Low-density parity-check codes have recently received much attention because of their excellent performance and the availability of a simple iterative decoder. The decoder, however, requires large amounts of Continue reading
A New Low Power 32×32-bit Multiplier
Multipliers are one of the most important building blocks in processors. This paper describes a low-power 32×32-bit parallel multiplier, designed and fabricated using Continue reading
An Asynchronous Pipelined 32×32-bit Iterative Multiplier Using Hybrid Handshaking Protocol
An asynchronous pipelined 32×32-bit iterative multiplier is presented in this paper. The multiplier supports 32×32-bit integer multiplication of both signed and Continue reading
A High Speed and Low Power VLSI Multiplier using a Redundant Binary Booth Encoding
This paper presents a new high speed and low power multiplier that uses a new encoding scheme, taking advantage of Continue reading
Continuous Occupancy Mapping Using Gaussian Processes
The topic of this thesis is occupancy mapping for mobile robots, with an emphasis on a novel method for continuous occupancy mapping using Continue reading
Low Power 32×32 bit Multiplier Architecture based on Vedic Mathematics Using Virtex 7 Low Power Device
In this paper the most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Continue reading
High-Speed and Low-Power Multipliers Using the Baugh-Wooley Algorithm and HPM Reduction Tree
The modified-Booth algorithm is extensively used for high-speed multiplier circuits. Once, when array multipliers were used, the reduced number of generated partial products significantly improved Continue reading
High Speed 16×16-bit Low-Latency Pipelined Booth Multiplier
This paper presents a high-speed 16×16-bit CMOS pipelined booth multiplier. Actually in an n-bit modified Booth multiplier, because of Continue reading