This Project “Automatic Night Lamp with Morning Alarm” was developed using Microprocessor. It is the Heart of the system. The sensors are made with help of LDR which are Light Dependent Resistors, whose Resistance is Continue reading
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Energy Saving Projects
Automatic Night Lamp with Morning Alarm – 2
Automatic Night Lamp with Morning Alarm System is a simple yet powerful concept, which uses transistor as a switch. By using this system manual works are 100% removed. It automatically switches ON lights when the sunlight goes Continue reading
BZ-FAD: A Low-Power Low-Area Multiplier based on Shift-and-Add Architecture
In this paper, a low-power structure called BZ-FAD (Bypass Zero, Feed A Directly) for shift-and-add multipliers is proposed. The architecture considerably lowers the Continue reading
Low Power and Low Complexity Shift-and-Add Based Computations
The main issue in this project is to minimize the energy consumption per operation for the arithmetic parts of DSP circuits, such as digital filters. More specific, the focus is on single- and multiple-constant multiplications, which are realized using Continue reading
A New Low Power 32×32-bit Multiplier
Multipliers are one of the most important building blocks in processors. This paper describes a low-power 32×32-bit parallel multiplier, designed and fabricated using Continue reading
Automatic Night Lamp with Morning Alarm – 1
This circuit automatically turns on a night lamp when bedroom light is switched off. The lamp remains ‘on’ until the light sensor senses daylight in the morning. A super-bright white LED is used as the night lamp. It gives Continue reading
An Asynchronous Pipelined 32×32-bit Iterative Multiplier Using Hybrid Handshaking Protocol
An asynchronous pipelined 32×32-bit iterative multiplier is presented in this paper. The multiplier supports 32×32-bit integer multiplication of both signed and Continue reading
A High Speed and Low Power VLSI Multiplier using a Redundant Binary Booth Encoding
This paper presents a new high speed and low power multiplier that uses a new encoding scheme, taking advantage of Continue reading
Low Power 32×32 bit Multiplier Architecture based on Vedic Mathematics Using Virtex 7 Low Power Device
In this paper the most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Continue reading
High-Speed and Low-Power Multipliers Using the Baugh-Wooley Algorithm and HPM Reduction Tree
The modified-Booth algorithm is extensively used for high-speed multiplier circuits. Once, when array multipliers were used, the reduced number of generated partial products significantly improved Continue reading
High Speed 16×16-bit Low-Latency Pipelined Booth Multiplier
This paper presents a high-speed 16×16-bit CMOS pipelined booth multiplier. Actually in an n-bit modified Booth multiplier, because of Continue reading