Division algorithms have been developed to reduce latency and to improve the efficiency of the processors. Floating point division is considered as a high latency operation. This papers looks into one such division algorithm, examines the hardware block diagram and suggests an alternative path which may be cost effective.
With the development in the computational complexity of the modern computer applications and the industry wide usage of benchmarks, such as SPECmarks, has forced the designers of the general purpose microprocessors to pay particular attention to the implementation of the floating point unit. S. Oberman and Flynn report that in most current processors, division is significantly slower than other operations.
Thus faster division algorithms are imperative for recent processors. Further, its very important for the hardware to be as simple as possible and should consume less area. Division algorithms are broadly classified into 2 classes: i. Digit Recurrence Methods and ii. Iterative and Quadratically convergent, considering Functional Iteration, Very High Radix, table lookup and variable latency to be one class.
Author: T. Dutta Roy
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