A VHDL Reaction Timer

This simple project will combine many advanced VHDL techniques including timers, seven segment display drivers, packages and functions, and state machines to create a simple game that to test a person’s reaction time.

A VHDL Reaction Timer – Reaction Timer Code:
library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.ALL;
USE work.bin_to_7seg.ALL;
ENTITY Lab5 IS
PORT(

50Mhz clock signal from the DE2 board
clk: IN std_logic;

KEY3 and KEY0 on the DE2 board
push_button
, reset: IN std_logic;

Outputs for the LEDS
LEDR, LEDG: OUT std_logic_vector(7 DOWNTO 0);

7 segment display outputs
digit1, digit2, digit3, digit4: OUT std_logic_vector(6 DOWNTO 0));
END;
ARCHITECTURE Lab5_beh of Lab5 IS

Type
definition for the four states used for the state machine
Type Timer_State IS (idle, countdown, timing, score);

Signals of type Timer_State used to control the state machine
SIGNAL current_state, next_state : Timer_State := idle;

16

bit bina
ry value of the elapsed time in milliseconds
SIGNAL elapsed_time: std_logic_vector(15 DOWNTO 0):= (OTHERS => ‘0’);

Flag that indicates the status of the countdown
SIGNAL countdown_done: std_logic := ‘0’;
Source: Michigan Technological University

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