An Asynchronous Pipelined 32×32-bit Iterative Multiplier Using Hybrid Handshaking Protocol

An asynchronous pipelined 32×32-bit iterative multiplier is presented in this paper. The multiplier supports 32×32-bit integer multiplication of both signed and un-signed operands. A 2-phase micropipeline latch controller is used which controls a 4-phase pipeline with standard transparent level sensitive latches.

The design employs the modified Booth algorithm diminishing 8 bits at a time with an iterative structure. A sign extension algorithm is also employed in this work. Furthermore, the early termination scheme speeds up the multiplication operation.

The multiplier consists of a total of 10700 CMOS elements and completes an 32×32-bit multiplication in 12ns under the typical conditions. This work is also very low power and costs only 50% energy per operation of that of Amulet3i multiplier.
Author: Neeraj Kumar Mishra | Subodh Wairya

Download Project

>> Energy Saving Project Ideas and Titles for Electrical & Electronics Engineering Students

Design of Low-Power High-Speed 32×32 Multiplier

>> 100+ Easy Electronics Projects for Engineering Students

Similar Projects:

For Free ECE/EEE Project Downloads:

Enter your email address:
( Its Free 100% )

Leave a Comment

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <s> <strike> <strong>