In this paper the most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Ancient Indian Vedic Mathematics.
As per this proposed architecture, for two 32-bit numbers; the multiplier and multiplicand, each are grouped as 16-bit numbers so that it decomposes into 16×16 multiplication modules.
It is also illustrated that the further hierarchical decomposition of 8×8 modules into 4×4 modules and then 2×2 modules will have a significant VHDL coding of for 32×32 bits multiplication and their used FPGA family Virtex 7 low power implementation by Xilinx Synthesis 16.1 tool done. The synthesis results show that the computation time for calculating the product of 32×32 bits is delay 29.256 ns. (11.499ns logic, 11.994ns route) (48.9% logic, 51.1% route).
INTRODUCTION TO MULTIPLIER:
Multiplication is a crucial unfussy, basic function in arithmetic procedures and Vedic mathematics is a endowment prearranged for the paramount of human race, due to the capability it bestows for quicker intellectual computation.
So multiplication is one of the most important operations in digital computer systems and digital signal processors. Beside multiplier is power hungry components so reducing their power dissipation satisfying the overall power budget of digital computer.
Source: IJRREST
Author: Neeraj Kumar Mishra | Subodh Wairya
Design of Low-Power High-Speed 32×32 Multiplier
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