A High Speed and Low Power VLSI Multiplier using a Redundant Binary Booth Encoding

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This paper presents a new high speed and low power multiplier that uses a new encoding scheme, taking advantage of a redundant binary addition.

The redundant binary representation is effective in speed, for it does not require carry propogation. The drawback is hardware increase due to the redundant bit.

In this paper, we introduce a novel redundant binary booth encoding scheme to eliminate the hardware overhead. Experimental results show that our multiplier exhibits the practical interest in high-speed and lower power designs.
Source: The Pennsylvania State University
Author: Jin-Hyuk Kim | Je-Huk Ryu | Jun-Dong Cho

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