Hardware Accelerator for Duo-binary CTC Decoding: Algorithm Selection, HW/SW Partitioning and FPGA Implementation

Wireless communication is always struggling with errors in the transmission. The digital data received from the radio channel is often erroneous due to thermal noise and fading. The error rate can be Continue reading

3D Image Segmentation Implementation on FPGA using EM/MPM Algorithm

In this Project, 3D image segmentation is targeted to a Xilinx Field Programmable Gate Array (FPGA), and verified with extensive simulation. Segmentation is performed using the Expectation-Maximization with Maximization of the Posterior Marginals (EM/MPM) Bayesian algorithm. This algorithm segments the Continue reading