A circuit design for a new high speed and Low Power 4-bit Braun Multiplier is presented. The multiplier is implemented by using different power reduction techniques. To design a Continue reading
Space, power consumption and speed are major design issues in VLSI circuit. The design component has conflicting affect on overall performance of circuits. An optimization of power dissipation can be achieved by Continue reading
This paper presents a new high speed and low power multiplier that uses a new encoding scheme, taking advantage of Continue reading
This paper proposes the design and implementation of Booth multiplier using VHDL. This compares the power consumption and delay of radix 2 and modified radix 4 Booth Continue reading
We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems.
Serial link transceivers achieve high offchip data rates by using multiplexing transmitters and demultiplexing receivers that interface parallel on-chip data paths with Continue reading
In this paper, we present a statistical method for estimating the peak power dissipation in VLSI circuits. The method is based on the theory of extreme order statistics applied to the probabilistic distributions of the cycle-by-cycle Continue reading