Physical Design of a Smart Camera with Integrated Digital Pixel Sensors Using a 0.13µm 8-Layer Metal CMOS Process

The design of cameras has historically kept imagery and computational circuitry isolated in an attempt to maximize image quality by improving pixel pitch and routing density. Although this technique has worked in creating high density arrays of Continue reading

Hardware Accelerator for Duo-binary CTC Decoding: Algorithm Selection, HW/SW Partitioning and FPGA Implementation

Wireless communication is always struggling with errors in the transmission. The digital data received from the radio channel is often erroneous due to thermal noise and fading. The error rate can be Continue reading