This project focuses on the design and simulation of a phase locked loop (PLL) integrated circuit. A PLL is an advanced topic and requires knowledge of control systems, analog and digital design, as well as communication basics to fully understand. A PLL often consists of a phase detector, low pass filter, and a voltage controlled
This project delves into each individual block of the full circuit and gives careful consideration to each, exploring
the different design techniques used to complete a PLL design. Although this particular circuit could be used for a number of different applications, this project focuses on the design of a PLL for simple clock generation.
Source: California Polytechnic State University
Authors: Scott Buchanan | Jonathan Bonello